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? semiconductor components industries, llc, 2011 may, 2011 ? rev. 2 1 publication order number: ncn8024/d ncn8024 smart card interface ic the ncn8024 is a single smart card interface ic. it is dedicated for 3.0 v/5.0 v smart card reader/writer applications. the device is fully compatible with the iso 7816 ? 3 and emv standards as well as with standards specifying conditional access in set ? to p ? box (stb) including nds. for details regarding device implementation refer to application note and8452/d, available upon request (please contact your local on semiconductor sales office or representative). features ? single ic card interface ? fully compatible with iso 7816 ? 3, emv and related standards including nds ? three bidirectional buffered i/o level shifters (c4, c7 and c8 card pins) ? 3.0 v or 5.0 v 5% regulated card power supply such as i cc 75 ma at 3.3 v v ddp 5.5 v ? independent power supply range on controller interface (2.7 v < v dd < 5.5 v) ? handles 3.0 v and 5.0 v smart cards ? thermal and short circuit protection on all card pins ? support up to 18 mhz clock with internal division ratio 1/1, 1/2, 1/4 and 1/8 through clkdiv1 and clkdiv2 pins ? esd protection on card pins up to 8 kv+ (human body model) ? activation/deactivation sequences (iso7816) ? fault protection mechanisms enabling automatic device deactivation in case of overload, overheating, card take ? off or power supply drop ? out ? interrupt signal int for card presence and faults ? external undervoltage lockout threshold adjustment on v dd (poradj pin) ? available in 2 package formats: soic ? 28 and tssop ? 28 ? these are pb ? free devices typical application ? set ? top boxes conditional access & pay ? tv ? conditional access modules (cam) ? pos / atm ? access control, identification see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information marking diagrams ncn8024 = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb ? free package http://onsemi.com soic ? 28 case 751f tssop ? 28 case 948aa 1 28 ncn8024 awlyywwg ncn 8024g alyw
ncn8024 http://onsemi.com 2 figure 1. typical smart card interface application c1 crd_vcc crd_aux1 crd_clk i/ouc crd_rst crd_pres vcc rst clk c4 gnd vpp i/o c8 det det gnd gnd 220 nf 1 2 3 4 5 6 7 8 smart card vdd vdd vddp 100 nf 100 nf clkdiv2 clkdiv1 gnd gndp crd_aux2 crd_gnd gnd crd_io 10 uf clkin aux1uc aux2uc poradj rstin vup 100 nf 100 nf 330 nf gnd vdd r1 r2 microcontroller dataport control int cmdvcc 5v/3v ncn8024 vddp c2 crd_pres figure 2. soic ? 28 and tss0p ? 28 pinout (top view) clkdiv1 clkdiv2 gndp c2 vddp c1 vup crd_pres crd_i/o crd_aux2 crd_aux1 crd_gnd cmdvcc aux2uc aux1uc i/ouc nc clkin gnd vdd rstin poradj crd_vcc crd_rst crd_clk int 5v/3v crd_pres 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
ncn8024 http://onsemi.com 3 figure 3. ncn8024 block diagram 23 3 19 18 1 2 24 25 26 28 27 20 22 9 10 5 7 17 4 8 15 16 11 13 12 14 21 6 clkdiv1 clkdiv2 gndp c2 vddp c1 vup crd_i/o crd_aux2 crd_aux1 crd_gnd cmdvcc aux2uc aux1uc i/ouc clkin gnd vdd rstin poradj crd_vcc crd_rst crd_clk int 5v/3v crd_pres nc crd_pres interrupt block card detection dc/dc converter internal oscillator 2.5 mhz supply voltage monitoring clock dividers control logic and sequencer card pin drivers thermal control pin function and description pin # name type description 1 clkdiv1 input this pin coupled with clkdiv2 is used to program the clock frequency division ratio (table 1). 2 clkdiv2 input this pin coupled with clkdiv1 is used to program the clock frequency division ratio (table 1). 3 5v/3v input allows selecting card v cc power supply voltage. crd_v cc = 5 v when 5v/3v = high or 3 v when 5v/3v = low 4 gndp gnd dc/dc converter power supply ground 5 c2 power dc/dc converter capacitor pin number 2 ? a 100 nf capacitor is connected between this pin and pin c1. the capacitor has to feature an esr lower than 100 m 6 vddp power dc/dc converter power supply voltage 7 c1 power dc/dc converter capacitor pin number 1 ? a 100 nf capacitor is connected between this pin and pin c2. the capacitor has to feature an esr lower than 100 m 8 vup power charge ? pump output ? a very low esr 100 nf capacitor (esr< 100 m ) is connected between this pin and gndp 9 crd_pres input card presence pin active (card present) when crd_pres = low. a built ? in debounce timer of about 8 ms is activated when a card is inserted. 10 crd_pres input card presence pin active (card present) when crd_pres = high. a built ? in debounce timer of about 8 ms is activated when a card is inserted.
ncn8024 http://onsemi.com 4 pin function and description pin # description type name 11 crd_i/o input/ output this pin handles the connection to the serial i/o (c7) of the card connector. a bi ? directional level translator adapts the serial i/o signal between the card and the micro controller. an 11 k (typical) pullup resistor to crd_v cc provides a high impedance state for the smart card i/o link. 12 crd_aux2 input/ output this pin handles the connection to the chip card?s serial auxiliary aux2 i/o pin (c8). a bi ? directional level translator adapts the serial i/o signal between the card and the micro controller. an 11 k (typical) pullup resistor to crd_v cc provides a high impedance state for the smart card c8 pin. 13 crd_aux1 input/ output this pin handles the connection to the chip card?s serial auxiliary aux1 i/o pin (c4). a bi ? directional level translator adapts the serial i/o signal between the card and the micro controller. an 11 k (typical) pullup resistor to crd_v cc provides a high impedance state for the smart card c4 pin. 14 crd_gnd gnd card ground 15 crd_clk output this pin is connected to the clock card connector?s pin (chip card?s pin c3). the clock signal comes from the clkin input through clock dividers and level shifter. 16 crd_rst output this pin is connected to the chip card?s reset pin (c2) through the card connector. a level translator adapts the external reset (rstin) signal to the smart card. 17 crd_vcc power this pin is connected to the smart card power supply pin. an internal dc/dc converter is programmable using the pin 5v/3v to supply either 5 v or 3 v output voltage. an external distributed ceramic capacitor (200 nf + 330 nf typical recommended) must be connected across crd_v cc and crd_gnd. this set of capacitor (if distributed) must be low esr (< 100 m ). 18 poradj input power ? on reset threshold adjustment input pin for changing the reset threshold with an external resistor power divider. recommended to be connected to ground when unused. 19 cmdvcc input command vcc pin. activation sequence enable/disable pin (active low). the activation sequence is enabled by toggling cmdvcc high to low and when a card is present. 20 rstin input this reset input connected to the host and referred to v dd (microcontroller side), is connected to the smart card reset pin through the internal level shifter which translates the level according to the crd_v cc programmed value. 21 vdd power this pin is connected to the system controller power supply. it configures the level shifter input stage to accept the signals coming from the controller. a 0.1 f capacitor shall be used to bypass the power supply voltage. when v dd is below 2.35 v typical the card pins are disabled. 22 gnd gnd ground 23 int output the interrupt request is activated low on this pin. this is enabled when a card is present and the card presence is detected by crd_pres or crd_pres pins. similarly an interrupt is generated when crd_v cc is overloaded. 20 k typical integrated pullup resistor to v dd . 24 clkin input clock input for external clock 25 nc unconnected 26 i/ouc input/ output this pin is connected to an external micro ? controller. a bi ? directional level translator adapts the serial i/o signal between the smart card and the external controller. a built ? in constant 11 k (typical) resistor provides a high impedance state. 27 aux1uc input/ output this pin is connected to an external micro ? controller. a bi ? directional level translator adapts the serial c4 signal between the smart card and the external controller. a built ? in constant 11 k (typical) resistor provides a high impedance state. 28 aux2uc input/ output this pin is connected to an external micro ? controller. a bi ? directional level translator adapts the serial c8 signal between the smart card and the external controller. a built ? in constant 11 k (typical) resistor provides a high impedance state.
ncn8024 http://onsemi.com 5 attributes characteristics values esd protection human body model (hbm) (note 1) card pins (card interface pins 9 ? 17) all other pins machine model (mm) card pins (card interface pins 9 ? 17) all other pins 8 kv 2 kv 400 v 150 v moisture sensitivity (note 2) soic ? 28 and tssop ? 28 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in meets or exceeds jedec spec eia/jesd78 ic latch ? up test 1. human body model (hbm), r = 1500 , c = 100 pf. 2. for additional information, see application note and8003/d. maximum ratings (note 3) rating symbol value unit dc/dc converter power supply voltage v ddp ? 0.3 v ddp 5.5 v power supply from microcontroller side v dd ? 0.3 v dd 5.5 v external card power supply crd_v cc ? 0.3 crd_v cc 5.5 v charge pump output v up ? 0.3 v up 5.5 digital input pins v in ? 0.3 v in v dd v digital output pins (i/ouc, aux1uc, aux2uc, int ) v out ? 0.3 v out v dd v smart card output pins v out ? 0.3 v out crd_v cc v thermal resistance junction ? to ? air soic ? 28 tssop ? 28 r ja 75 76 c/w operating ambient temperature range t a ? 40 to +85 c operating junction temperature range t j ? 40 to +125 c maximum junction temperature t jmax +125 c storage temperature range t stg ? 65 to + 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = +25 c
ncn8024 http://onsemi.com 6 power supply section (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) pin symbol rating min typ max unit 6 v ddp dc/dc converter power supply, crd_v cc = 3 v and 5 v with dc load such as |i cc | 75 ma |i cc | 20 ma 3.3 3.0 5.0 5.5 5.5 v 6 v ddp nds conditions: dc/dc converter power supply, crd_v cc = 3 v and 5 v with 75 ma load transient from 100 hz to 200 mhz and /cmdvcc cycling (note 4): |i cc | 75 ma |i cc | 20 ma 4.5 3.15 5.0 5.5 5.5 v 6 i ddp inactive mode ? ? 0.3 ma 6 i ddp dc operating supply current, f clkin = 10 mhz, cout crd_clk = 33 pf, ? i crd_vcc ? = 0 ? ? 5.0 ma 6 i ddp dc operating supply current, crd_v cc = 5 v, i crd_vcc = 75 ma crd_v cc = 3 v, i crd_vcc = 75 ma ? ? 200 200 ma 21 v dd operating voltage 2.7 ? 5.5 v 21 i vdd inactive mode 0 standby current ? ? 0.6 ma 21 i vdd operating current ? f clk_in = 10 mhz, cout crd_clk = 33 pf, ? i crd_vcc ? = 0 ? ? 1 ma 21 uvlov dd undervoltage lockout (uvlo), no external resistor at pin poradj (connected to gnd), falling v dd level 2.25 2.35 2.45 v 21 uvlohys uvlo hysteresis, no external resistor at pin poradj (connected to gnd) 50 130 180 mv poradj pin 18 v porth+ external rising threshold voltage on v dd for power on reset ? pin poradj 1.18 1.24 1.3 v 18 v porth ? external falling threshold voltage on v dd for power on reset ? pin poradj 1.13 1.18 1.24 v 18 v porhys hysteresis on v porth (pin poradj) 30 60 100 mv 18 t por width of power ? on reset pulse (note 4) no external resistor on poradj external resistor on poradj 4 4 8 8 12 12 ms 18 i il low level input leakage current, v il <0.5 v (pulldown current source) 5 a dc/dc converter f clk dc/dc converter clock frequency when card active (note 4) 2.2 3.2 mhz 8 v up output voltage on pin v up (average value) crd_v cc = 5v crd_v cc = 3v 5.0 5.0 5.23 5.23 5.5 5.5 v 17 c crd_vcc output capacitance on card power supply crd_v cc (notes 4 and 5) 300 220 + 320 1000 nf 17 crd_v cc output card supply voltage @ 4.5 v< v ddp < 5.5 v (including ripple) crd_v cc = 3.0 v @ i load 65 ma crd_v cc = 5.0 v @ i load 65 ma 2.85 4.75 3.00 5.00 3.15 5.25 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. guaranteed by design and characterization 5. these values take into account the tolerance of the cms capacitor used. the allowed values are single or distributed capacitor combin ation not exceeding 1.0 f with 220 nf + 330 nf typical and recommended. it is recommended to use x5r or x7r ? type capacitors with very low esr (< 100 m ) for optimal performances.
ncn8024 http://onsemi.com 7 power supply section (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) pin unit max typ min rating symbol dc/dc converter 17 crd_v cc output card supply voltage @ 3.6 v v ddp 5.5 v with |i cc | 65 ma load transient from 100 hz to 200 mhz (including ripple) (note 4) crd_v cc = 3.0 v crd_v cc = 5.0 v 2.76 4.65 3.00 5.00 3.20 5.25 v v 17 crd_v cc output card supply voltage @ 4.5 v< v ddp < 5.5 v with current ? load pulses of 40 nas/t < 400 ns and |i cc | < 200 ma peak current (including ripple) (note 4) crd_v cc = 3.0 v crd_v cc = 5.0 v 2.76 4.65 3.00 5.00 3.20 5.25 v v 17 i crd_vcc card supply current @ crd_v cc = 3.0 v @ crd_v cc = 5.0 v 75 75 ma 17 i crd_vcc_sc short ? circuit current ? crd_v cc shorted to ground 110 150 ma 17 v crd_vcc output card supply voltage ripple peak ? to ? peak ? f ripple = 100 hz to 200 mhz (load transient with 65 ma peak current) (note 4) 350 mv 17 crd_v ccsr slew rate on crd_v cc up or down (note 4) 0.22 v/ s note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. guaranteed by design and characterization 5. these values take into account the tolerance of the cms capacitor used. the allowed values are single or distributed capacitor combin ation not exceeding 1.0 f with 220 nf + 330 nf typical and recommended. it is recommended to use x5r or x7r ? type capacitors with very low esr (< 100 m ) for optimal performances. digital input/output section clkin, rstin, i/ouc, aux1uc, aux2uc, clkdiv1, clkdiv2, cmdvcc , 5v/3v (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) pin symbol rating min typ max unit 24 f clkin clock frequency on pin clkin (with divider ratio 2) (note 6) ? ? 27 mhz 1, 2, 3, 19, 20, 24, 26, 27, 28 v il input voltage level low: clkin, rstin, i/ouc, aux1uc, aux2uc, clkdiv1, clkdiv2, cmdvcc , 5v/3v ? 0.3 ? 0.3 x v dd v 1, 2, 3, 19, 20, 24, 26, 27, 28 v ih input voltage level high: clkin, rstin, i/o, aux1, aux2, clkdiv1, clkdiv2, cmdvcc , 5v/3v 0.7 x v dd ? v dd + 0.3 v 1, 2, 3, 19, 20, 24 i il clkdiv1, clkdiv2, cmdvcc , rstin, clkin, 5v/3v low level input leakage current, v il = 0 v ? ? 1.0 a 1, 2, 3, 19, 20, 24 i ih clkdiv1, clkdiv2, cmdvcc , rstin, clkin, 5v/3v low level input leakage current, v ih = v dd ? ? 1.0 a 26, 27, 28 i il i/ouc, aux1uc, aux2uc low level input leakage current, v il = 0 v ? ? 600 a 26, 27, 28 i ih i/ouc, aux1uc, aux2uc high level input leakage current, v ih = v dd ? ? 10 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. guaranteed by design and characterization
ncn8024 http://onsemi.com 8 digital input/output section clkin, rstin, i/ouc, aux1uc, aux2uc, clkdiv1, clkdiv2, cmdvcc , 5v/3v (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) pin unit max typ min rating symbol 26, 27, 28 v oh v ol t ri/fi t ro/fo i/ouc, aux1uc, aux2uc data channels, @ cs 30 pf high level output voltage (crd_i/o = crd_aux1 = crd_aux2 = crd_v cc )i oh = 0 i oh = ? 40 a low level output voltage (c_i/o= crd_aux1 = crd_aux2 = 0 v) i ol = +1 ma input rising/falling times (note 6) output rising/falling times (note 6) 0.9 x v dd 0.75 x v dd 0 ? ? ? ? ? ? ? v dd + 0.1 v dd + 0.1 0.3 1.2 0.1 v v v s s 26, 27, 28 f bidi maximum frequency through bidirectional i/o, aux1 and aux2 channels (note 6) ? ? 1 mhz 26, 27, 28 r pu i/0uc, aux1uc, aux2uc pullup resistor 8.0 11 16 k 23 v oh output high voltage int @ i oh = ? 15 a (source) 0.75 x v dd ? ? v 23 v ol output low voltage int @ i ol = 2 ma (sink) 0 ? 0.30 v 23 r int int pullup resistor 14 20 26 k note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. guaranteed by design and characterization
ncn8024 http://onsemi.com 9 smart card interface section, crd_io, crd_aux1, crd_aux2, crd_clk, crd_rst, crd_pres, crd_pres (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) pin symbol rating min typ max unit 16 v oh v ol v oh v ol t r t f t d crd_rst @ crd_v cc = 3.0 v, 5.0 v output reset v oh @ i rst = ? 200 a output reset v ol @ i rst = 200 a output reset v oh @ i rst = ? 20 ma output reset v ol @ i rst = 20 ma output reset risetime @ c out = 100 pf (note 7) output reset falltime @c out = 100 pf (note 7) rstin to crd_rst delay ? reset enabled (note 7) 0.9 x crd_v cc 0 0 crd_v cc ? 0.4 ? ? ? ? ? ? ? ? ? ? crd_v cc 0.20 0.4 crd_v cc 100 100 2 v v v v ns ns s 15 f crdclk v oh v ol v oh v ol f dc t rills t ulsa sr crd_clk @ crd_v cc = 3.0 v or 5.0 v output frequency (note 7) output crd_clk v oh @ i clk = ? 200 a output crd_clk v ol @ i clk = 200 a output crd_clk v oh @ i clk = ? 70 ma output crd_clk v ol @ i clk = 70 ma output duty cycle (note 7) rise & fall time (note 5) output crd_clk risetime @ c out = 30 pf output crd_clk falltime @ c out = 30 pf slew rate @ cout = 33 pf (note 7) ? 0.9 x crd_v cc 0 0 crd_v cc ? 0.4 45 ? ? 0.2 ? ? ? ? ? ? ? ? ? 18 crd_v cc +0.2 0.4 crd_v cc 55 16 16 ? mhz v v v v % ns ns v/ns 11, 12, 13 v ih v ih v il i il i ih v oh v ol t ri/fi t ro/fo crd_aux1, crd_aux2, crd_io @ crd_v cc = 3.0 v, 5.0 v input voltage high level (5 v mode) input voltage high level (3 v mode) input voltage low level low level input current v il = 0 v high level input current v ih = crd_v cc output v oh @ i oh = ? 40 a output v ol @ i ol = 1 ma, v il = 0 v input rising/falling times output rising/falling times / c out = 80 pf 2.5 1.6 0.30 ? ? 0.75 x crd_v cc 0 ? ? ? ? ? ? ? ? ? ? crd_v cc +0.3 crd_v cc +0.3 0.80 600 10 crd_v cc +0.1 0.30 1.2 0.1 v v v a a v v s s 11, 12, 13 r pu crd_aux1, crd_aux2, crd_io pullup resistor 8.0 11 16 k t io propagation delay i ouc ? > crd_io and crd_io ? > iouc (falling edge) (note 7) ? ? 200 ns t pu active pull ? up pulse width buffers i/o, aux1 & aux2 (note 7) ? 200 ? ns 9, 10 v ih v il crd_pres, crd_pres card presence voltage high level card presence voltage low level 0.7 x v dd ? 0.3 v dd + 0.3 0.3 x v dd v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. guaranteed by design and characterization
ncn8024 http://onsemi.com 10 smart card interface section, crd_io, crd_aux1, crd_aux2, crd_clk, crd_rst, crd_pres, crd_pres (v dd = 3.3 v; v ddp = 5 v; t amb = 25 c; f clkin = 10 mhz) pin unit max typ min rating symbol 9, 10 |i ih | |i il | crd_pres, crd_pres low level input leakage current, v ih = v dd crd_pres crd_pres high level input leakage current, v il = 0 v crd_pres crd_pres 5 5 10 1 1 10 a 9, 10 t debounce debounce time crd_pres and crd_pres (note 7) 5 8 11 ms 11, 12, 13, 16 i crd_io crd_io, crd_aux1, crd_aux2 current limitation ? ? 15 ma 15 i crd_clk crd_clk current limitation ? ? 70 ma 16 i crd_rst crd_rst current limitation ? ? 20 ma t act activation time (note 7) 30 ? 100 s t deact deactivation time (note 7) 30 ? 250 s temp sd shutdown temperature ? 160 ? c note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. guaranteed by design and characterization power supply the ncn8024 smart card interface has two power supplies: v dd and v ddp . v dd is usually common to the system controller and the interface. the applied v dd ranges from 2.7 v up to 5.5 v. if v dd goes below 2.35 v typical (uvlo vdd ) a power ? down sequence is automatically performed. in that case the interrupt (int ) pin is set low. a built ? in charge ? pump ? based dc/dc converter followed by a low drop ? out (ldo) regulator is used to provide the 3 v or 5 v power supply voltage (crd_v cc ) to the card. v ddp is the converter?s input voltage. vup is the charge ? pump converter?s output. it is connected to the ldo input. a reservoir capacitor of 100 nf is connected to vup. crd_v cc is the ldo output. even if the converter can operate with a single output reservoir capacitor as low as 100 nf at crd_v cc , it is recommended to use a capacitor of at least 320 nf in order to satisfy the datasheet specifications. the best recommended combination guaranteeing optimal performances consists in a distributed set of capacitors 220 nf + 330 nf (in particular recommended for optimally satisfying the nds standard). to minimize di/dt effects, the fly capacitor (100 nf) and the reservoir capacitors vup and crd_v cc have to be connected as close as possible to the corresponding device?s pin and feature very low esr values (lower than 50 m ). the fly capacitor is connected between c1 and c2. the decoupling capacitors on v dd and v ddp respectively 100 nf and 10 f have also to be connected close to the respective ic pins. the crd_vcc pin can source up to 75 ma continuously over the v ddp range (from 3.3 v to 5.5 v), the absolute maximum current being internally limited below 150 ma (typical at 110 ma). crd_vcc can stay in the range 4.6 v ? 5.30 v during current transient up to 200 ma (peak current) over less than 400 ns of current pulse duration such as the charge transient is lower than 40 nas. there?s no specific sequence for applying v dd or v ddp . they can be applied to the interface in any sequence. after powering the device int remains low until a card is inserted. supply voltage monitoring the supply voltage monitoring block includes the power on reset (por) circuitry and the under voltage lockout (uvlo) detection (v dd voltage dropout detection). poradj pin allows the user, according to the considered application, to adjust the v dd uvlo threshold. if not used poradj pin is connected to ground. the input supply voltage is continuously monitored to prevent under voltage operation. at power up, the system initializes the internal logic during por timing and no further signal can be provided or supported during this period. such initialization takes place when the input voltage rises between 2 v to 2.6 v about typical. the system is ready to operate when the input voltage has reached the minimum 2.7 v. considering this, the ncn8024 will detect an under ? voltage situation when the input supply voltage will drop below 2.35 v typical. when v dd goes down below the uvlo falling threshold a deactivation sequence is performed. the device is inactive during power ? on and power ? off of the v dd supply (8 ms reset pulse).
ncn8024 http://onsemi.com 11 poradj pin is used to modify the uvlo threshold according to the below relationship considering an external resistor divider r1 / r2 (see block diagram figure 1): uvlo r1 r2 r2 v por if poradj is connected to ground the v dd uvlo threshold (v dd falling) is typically 2.35 v. in some cases it can be interesting to adjust this threshold at a higher value and by the way increase the v dd supply dropout detection level which enables a deactivation sequence if the v dd voltage is too low. for example, there are microcontrollers for which the minimum supply voltage insuring a correct operating is higher than 2.55 v, increasing uvlo vdd (v dd falling) is consequently necessary. considering for instance a resistor bridge with r1 = 56 k , r2 = 42 k and v por ? = 1.18 v typical the v dd dropout detection level can be increased up to: uvlo 59k 42k 42k v por ? 2.75 v the minimum dropout detection voltage should be higher than 2 v. the maximum detection level may be up to vdd. clock divider: the input clock can be divided by 1/1, 1/2, 1/4, or 1/8, depending upon the specific application, prior to be applied to the smart card driver. these division ratios are programmed using pins clkdiv1 and clkdiv2 (see table 1). the input clock is provided externally to pin clkin. table 1. clock frequency programming clkdiv1 clkdiv2 f crd_clk 0 0 clkin/8 0 1 cklkin / 4 1 0 clkin 1 1 clkin / 2 the clock input stage (clkin) can handle a 27 mhz maximum frequency signal (considering a division ratio 2). of course, the ratio must be defined by the user to cope with smart card considered in a given application in order to avoid any duty cycle out of the 45% / 55% range specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio 1/2, 1/4 or 1/8. on the other hand, the output signal duty cycle cannot be guaranteed 50% if the division ratio is 1 and if the input duty cycle signal is not within the 46 ? 56% range at the clkin input. when the signal applied to clkin is coming from the external controller, the clock will be applied to the card under the control of the microcontroller or similar device after the activation sequence has been completed. data i/o, aux1 and aux2 level shifters the three bidirectional level shifters i/o, aux1 and aux2 adapt the voltage difference that might exist between the micro ? controller and the smart card. these three channels are identical. the first side of the bidirectional level shifter dropping low (falling edge) becomes the driver side until the level shifter enters again in the idle state pulling high crd_io and i/ouc. passive 11 k pull ? up resistors have been internally integrated on each terminal of the bidirectional channel. in addition with these pull ? up resistors, an active pull ? up circuit provides a fast charge of the stray capacitance. the current to and from the card i/o lines is limited internally to 15 ma and the maximum frequency on these lines is 1 mhz. standby mode after a power ? on reset, the circuit enters the standby mode. a minimum number of circuits are active while waiting for the microcontroller to start a session: ? all card contacts are inactive ? pins i/ouc, aux1uc and aux2uc are in the high ? impedance state (11 k pull ? up resistor to v dd ) ? card pins are inactive and pulled low ? supply voltage monitoring is active ? the internal dc/dc converter oscillator is running. power ? up in the standby mode the microcontroller can check the presence of a card using the signals int and cmdvcc as shown in table 2: table 2. card presence state int cmdvcc state high high card present low high card not present if a card is detected present (crd_pres or crd_pres active) the controller can start a card session by pulling cmdvcc low. card activation is run (t0, figure 5). this power ? up sequence makes sure all the card related signals are low during the crd_v cc positive going slope. these lines are validated when crd_v cc is stable and above the minimum voltage specified. when the crd_v cc voltage reaches the programmed value (3.0 v or 5.0 v), the circuit activates the card signals according to the following sequence (figure 5): ? crd_v cc is powered ? up at its nominal value (t1) ? i/o, aux1 and aux2 lines are activated (t2) ? then clock channel is activated and the clock signal is applied to the card (t3) ? finally the reset level shifter is enabled (t4)
ncn8024 http://onsemi.com 12 the clock can also be applied to the card using a rstin mode allowing controlling the clock starting by setting rstin low (figure 4). before running the activation sequence, that is before setting low cmdvcc rstin is set high. in these initial conditions crd_clk starts when rstin is pulled low. this allows a precise count of clock pulses before toggling crd_rst high for atr (answer to reset) request. the internal activation sequence activates the different channels according to a specific hardware built ? it sequencing internally defined but at the end the actual activation sequencing is the responsibility of the application software and can be redefined by the micro ? controller to comply with the different standards and the different ways the standards manage this activation (for example light differences exist between the emv and the iso7816 standards). figure 4. activation sequence ? rstin mode (rstin starting high) crd_rst crd_vcc crd_io crd_clk cmdvcc atr rstin t0 t1 t2 figure 5. activation sequence ? normal mode crd_rst crd_vcc crd_io crd_clk cmdvcc atr rstin t0 t1 t2 t3 t act t4
ncn8024 http://onsemi.com 13 power ? down when the communication session is completed the ncn8024 runs a deactivation sequence by setting high cmdvcc . the below power down sequence is executed: ? crd_rst is forced to low ? crd_clk is set low 12 s after crd_rst. ? crd_io, crd_aux1 and crd_aux2 are pulled low ? finally crd_v cc supply can be shut ? off. figure 6. deactivation sequence crd_rst crd_io crd_clk cmdvcc crd_vcc t deact fault detection in order to protect both the interface and the external smart card, the ncn8024 provides security features to prevent failures or damages as depicted here after. ? card extraction detection ? v dd under voltage detection ? short ? circuit or overload on crd_v cc ? card pin current limitation: in the case of a short circuit to ground. no feedback is provided to the external mpu. ? dc/dc operation: the internal circuit continuously senses the crd_v cc voltage (in the case of either over or under voltage situation). ? dc/dc operation: under ? voltage detection on v ddp or overload on vup ? overheating figure 7. fault detection and interrupt management debounce debounce powerdown caused by short ? circuit powerdown resulting of card extraction int crd_vcc crd_pres cmdvcc interrupt pin management: a card session is opened by toggling cmdvcc high to low. before a card session, cmdvcc is supposed to be in a high position. int is low if no card is present in the card connector (normally open or normally closed type). int is high if a card is present. if a card is inserted (int = high) and if v dd drops below the uvlo threshold then int pin drops low immediately. it turns back high when v dd increases again over the uvlo limit (including hysteresis), a card being still present. during a card session, cmdvcc is low and int pin goes low when a fault is detected. in that case a deactivation is immediately and automatically performed (see figure 6). when the microcontroller resets cmdvcc to high it can sense the int level again after having got completed the deactivation. as illustrated by figure 7 the device has a debounce timer of 8 ms typical duration. when a card is inserted, output int goes high only at the end of the debounce time. when the card is removed a deactivation sequence is automatically and immediately performed and int goes low.
ncn8024 http://onsemi.com 14 esd protection the ncn8024 includes devices to protect the pins against the esd spikes voltages. to cope with the different esd voltages developed across these pins, the built in structures have been designed to handle either 2 kv, when related to the micro controller side, or 8 kv when connected with the external contacts (hbm model). practically, the crd_rst, crd_clk, crd_io, crd_aux1, crd_aux2, crd_pres and crd_pres pins can sustain 8 kv. the crd_vcc pin has the same esd protection and can source up to 75 ma continuously, the absolute maximum current being internally limited with a max at 150 ma. the crd_vcc current limit depends on v ddp and crd_vcc. figure 8. application schematic clkdiv1 clkdiv2 gndp c2 vddp c1 vup crd_pres crd_i/o crd_aux2 crd_gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 clkin nc aux2uc vdd i/ouc aux1uc gnd crd_clk crd_vcc crd_rst poradj rstin ncn8024 3.3 v microcontroller vcc rst clk c4 gnd vpp i/o c8 1 2 3 4 5 6 7 8 smart card r1 r2 vdd +3.3v det normally open 100 nf vdd +3.3v 100 nf 330 nf vddp 100 nf + 100 nf 220 nf xtal1 xtal2 optional r1/r2 resistor divider ? connected to ground 10 f 5v/3v 100 k crd_aux1 crd_pres +3.3v +5v or if not used poradj has to be int cmdvcc ordering information device package shipping ? NCN8024DWR2G soic ? 28 (pb ? free) 1000 / tape & reel ncn8024dtbr2g tssop ? 28 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *consult sales office
ncn8024 http://onsemi.com 15 package dimensions soic ? 28 wb case 751f ? 05 issue h 11.00 28x 0.52 28x 1.30 1.27 dimensions: millimeters 1 pitch 28 14 15 8x a1 1 15 14 28 b s x m 0.025 y s t m 0.25 y m seating plane a dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 g 1.27 bsc h 10.05 10.55 l 0.41 0.90 m 0 8 l c pin 1 ident d e h 0.10 ? x ? ? y ? g ? t ? m notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold protrusion 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable damber pr5otrusion shall not be 0.13 totatl in excess of b dimension at maximum material condition. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncn8024 http://onsemi.com 16 package dimensions ????? ????? ????? 0.20 a e ??? ??? ??? ? a 0.25 15 28 14 pin one location notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the ?b? dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. b e e1 b c 1 0.10 seating a c d c plane 0.05 a a2 a1 b 28x 0.10 a b c a a detail a dim min max millimeters a ??? 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 b1 0.19 0.25 c 0.09 0.20 c1 0.09 0.16 d 9.60 9.80 e 6.40 bsc e1 4.30 4.50 e 0.65 bsc l 0.45 0.75 l1 1.00 ref r 0.09 ??? r1 0.09 ??? s 0.20 ??? 01 0 8 02 12 ref 03 12 ref l 03 01 r r1 s 02 h gauge plane (b) b1 c1 c 2x 28 lead tssop case 948aa ? 01 issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncn8024/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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